This invention relates to circuit analyzers. In particular, this invention relates to circuit analyzers performing static analysis of circuits including black box timing models.
Circuit analyzers in the art fall into one of two general categories: dynamic and static. With dynamic analyzers, the design or diagnostic engineer must provide sets of waveforms to simulate the conditions under which a circuit will operate. Of course, the more the sets reflect all possible operating conditions, the more accurate the result of the dynamic analysis can be. The cost, however, of producing exhaustive waveform sets can be extremely high.
Static analyzers, on the other hand, relieve the design engineer of the trouble of supplying comprehensive input vectors. A static analyzer can identify critical paths in a circuit, find timing errors and estimate overall performance. This waveform independence is particularly efficient and useful for large systems. Such static analyzers can identify critical paths which the test patterns do not exercise during timing simulation.
Abstracting a section of a circuit into a block timing model can be useful. Block models allow circuit analyzers to verify a large circuit at a chip level, with attendant savings in time to perform the analysis. A timing model can also serve as a communication tool between different groups of designers since the model provides a simple way to describe the operation of the circuit section and to check the interfaces between different design blocks. Each of the design groups will generate a timing model for its own block and will roll it up to full chip timing.
The most common block timing model that has been used for this purpose is the black box model. There are two types of paths in a black box: combinatorial or latched. A combinatorial path proceeds from an input pin of the black box to an output pin, passing through only combinatorial logic. A black box models combinatorial paths as pin-to-pin delays. Latched paths, however, are a convergence of data and clock inputs onward to an output pin. The black box models these latched paths using setup and hold times. A black box model can also include slope- and load-dependent delays with respect to the driving of an input or output pin.
In a black box model, the modeler derives setup and hold times for an input pin from the first or most critical (i.e., restrictive) latch in the latched path from that input pin. FIG. 1 shows a latch for which a modeler would derive setup and hold times. Latch 10 has data input 5 and clock input 6. Clock signal 4, with leading (opening) edge 1 and trailing (closing) edge slope 2, is a typical waveform for input on clock input 6. (Clock signal 4 is active HIGH.) The black box modeler can make the setup time a function of leading edge 1 of clock signal 4 or a function of trailing edge 2 of clock signal 4. In the former case, input on data input 5 must arrive at latch 10 before clock signal 4 goes active. In the latter case, the latch can sample data after leading edge 1 arrives at the latch.
The main disadvantage of black box modelling is that the modelling does not support latch transparency. FIG. 2 shows a sequence of black boxes which can illustrate the limitations of black box modelling. FIG. 2 shows a first black box model, block A, with an output signal n1 coupled as an input to a second black box model, block B. Block B itself has an output, signal n2, coupled as an input to the third black box model, block C. Assume that a data signal goes from block A to block C through latches internal to block B. If a circuit analyzer detects a setup time violation on signal n2, then the design engineer must involve block B in the effort to correct the violation. If, however, there is spare time on the input of block B, signal n1, the engineer might desire to borrow or transfer that spare time from signal n1 to signal n2. If this is possible, then the engineer need not change block B. With black box modelling, the designer will have to do this time borrowing manually and will have to generate a new model that reflects this time borrowing. Black box modelling does not permit a latch to sample data after the leading edge of the clocking signal.
Accordingly, it is an object of this invention to provide a solution for latch transparency in timing models.
In the design cycle of a circuit, clock waveforms very often change due to changes in the layout of the design. Such a change in a clock waveform may require the designers to re-verify large portions of the design.
Accordingly, it is another object of this invention to enable verification of a circuit without abandoning block-level modelling and without regenerating a timing model.
In order to check for internal violations of design parameters, a design engineer using black box block models would typically wait until each block was replaced with its device-level equivalent. Using device-level equivalents first requires that each group of designers complete its respective device-specific implementation of its block.
Accordingly a goal of this invention to permit the checking of paths internal to block models without descending to a device-level circuit.
These and other objects and goals of this invention will be readily apparent to those of skill in the art on reading the disclosure below.